A master's thesis at the College of Engineering at the University of Basrah examined (a common decimal and binary unit for the combined multiplication-addition process with a floating-point using redundant number systems) by the student Muhammad Nabil Jassim
The thesis dealt with reducing the time delay in the critical path. This architecture relies on the complex multiplication unit for the floating-point and binary systems that uses excess addition methods, combining the redundant and binary redundant decimal coding systems, generating partial multiples of the decimal system in the form of a binary decimal system and a new model for distributing partial multiples On the whole shorthand tree
The architecture of the integrated multiplication-addition unit can be divided into four stages
Also, the arithmetic operations for addition and rounding were performed in one step instead of two successive steps using a common module for addition and rounding to increase the speed of performance of this architecture.
Rounding controller selects the correct output, and a simple post-correction logic circuit is used to adjust the correct output when its digits are outside the decimal limit.
